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r ds004 (v. 1.3) october 4, 1999 - product speci?cation 6-171 XC4000XLA/xv field programmable gate arrays 6 xc4000 xla speci?cation information de?nition of terms in the following tables, some speci?cations may be designated as advance or preliminary. these terms are de?ned as follows: advance: initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. values are subject to change. use as estimates, not for production. preliminary: based on preliminary characterization. further changes are not expected. unmarked: speci?cations not identi?ed as either advance or preliminary are to be considered ?nal. all speci?cations are subject to change without notice. additional speci?cations except for pin-to-pin input and output parameters, the ac parameter delay speci?cations included in this document are derived from measuring internal test patterns. all speci?cations are representative of worst-case supply voltage and junction temperature conditions. the parameters included are common to popular designs and typical applications. XC4000XLA d.c. characteristic guidelines absolute maximum ratings recommended operating conditions symbol description values units v cc supply voltage relative to gnd -0.5 to 4.0 v v in input voltage relative to gnd (note 1) -0.5 to 5.5 v v ts voltage applied to 3-state output (note 1) -0.5 to 5.5 v v cct longest supply voltage rise time from 1 v to 3v 50 ms t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 c t j junction temperature ceramic packages +150 c plastic packages +125 c notes: 1. maximum dc overshoot or undershoot above v cc or below gnd must be limited to either 0.5 v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to -2.0 v or overshoot to + 7.0 v, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. 2. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc supply voltage relative to gnd, t j = 0 c to +85 c commercial 3.0 3.6 v supply voltage relative to gnd, t j = -40 c to +100 c industrial 3.0 3.6 v v ih high-level input voltage 50% of v cc 5.5 v v il low-level input voltage 0 30% of v cc v t in input signal transition time 250 ns note: at junction temperatures above those listed as operating conditions, all delay parameters increase by 0.35% per c. input and output measurement threshold is ~50% of v cc .
r XC4000XLA/xv field programmable gate arrays 6-172 ds004 (v. 1.3) october 4, 1999 - product speci?cation dc characteristics over recommended operating conditions power-on power supply requirements xilinx fpgas require a minimum rated power supply current capacity to insure proper initialization, and the power supply ramp rate does affect the current required. a fast ramp rate requires more current than a slow ramp rate. the slowest ramp rate is 50 ms with no speci?cations for a ramp rate faster than 2 ms. symbol description min max units v oh high-level output voltage @ i oh = -4.0 ma, v cc min (lvttl) 2.4 v high-level output voltage @ i oh = -500 m a, (lvcmos) 90% v cc v v ol low-level output voltage @ i ol = 24.0 ma, v cc min (lvttl) (note 1) 0.4 v low-level output voltage @ i ol = 1500 m a, (lvcmos) 10% v cc v v dr data retention supply voltage (below which configuration data may be lost) 2.5 v i cco quiescent fpga supply current (note 2) 10 ma i l input or output leakage current -10 +10 m a c in input capacitance (sample tested) bga, sbga, pq, hq, mq packages 10 pf pga packages 16 pf i rpu pad pull-up (when selected) @ v in = 0 v (sample tested) 0.02 0.25 ma i rpd pad pull-down (when selected) @ v in = 3.6 v (sample tested) 0.02 0.15 ma i rll horizontal longline pull-up (when selected) @ logic low 0.3 2.0 ma notes: 1. with up to 64 pins simultaneously sinking 24 ma 2. with no output current loads, no active input or longline pull-up resistors, all i/o pins tri-stated and ?oating product description ramp rate fast (120 m s) slow (50 ms) XC4000XLA family minimum required current supply 500 ma 500 ma notes: fast condition is tested at factory only. slow condition is tested at both wafer sort and factory. all limits are based on vcc trip setting. peak current is not measured. devices are guaranteed to initialize properly with the minimum current listed above. a larger capacity power supply may result in a larger initialization current. this speci?cation applies to commercial and industrial grade products only.
r ds004 (v. 1.3) october 4, 1999 - product speci?cation 6-173 XC4000XLA/xv field programmable gate arrays 6 xc4000 xla switching characteristics testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb ?ip-?ops are clocked by the global clock net. when fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature. values apply to all XC4000XLA devices and expressed in nanoseconds unless otherwise noted. delay via global low skew clock buffer to clock delay via fastclk buffer to iob clock speed grade all -09 -08 -07 units description symbol device min max max max delay from pad through global low skew (gls) clock buffer to any clock input, k. t gls xc4013xla 0.7 2.4 2.1 1.9 ns xc4020xla 0.7 2.6 2.3 2.1 ns xc4028xla 0.8 2.9 2.6 2.3 ns xc4036xla 0.8 3.2 2.8 2.5 ns xc4044xla 0.9 3.6 3.1 2.8 ns xc4052xla 1.0 3.9 3.4 3.1 ns xc4062xla 1.1 4.2 3.7 3.3 ns xc4085xla 1.2 5.0 4.4 3.9 ns preliminary speed grade all -09 -08 -07 units description symbol device min max max max delay from pad through fastclk buffer to any iob clock input. t fclk xc4013xla 0.4 1.5 1.3 1.1 ns xc4020xla 0.5 1.5 1.3 1.2 ns xc4028xla 0.5 1.6 1.4 1.3 ns xc4036xla 0.5 1.7 1.5 1.4 ns xc4044xla 0.5 1.8 1.6 1.4 ns xc4052xla 0.6 1.9 1.7 1.5 ns xc4062xla 0.6 2.0 1.8 1.6 ns xc4085xla 0.6 2.3 2.0 1.8 ns note: values in bold face are preliminary, all other values are advance. preliminary
r XC4000XLA/xv field programmable gate arrays 6-174 ds004 (v. 1.3) october 4, 1999 - product speci?cation delay via global early bufges 1, 2, 5, 6 to iob clock delay via global early bufges 3, 4, 7, 8 to iob clock speed grade all -09 -08 -07 units description symbol device min max max max delay from pad through global early (ge) clock buffer to any iob clock input for bufges 1, 2, 5, and 6. t ge xc4013xla 0.2 1.7 1.5 1.3 ns xc4020xla 0.2 1.9 1.7 1.5 ns xc4028xla 0.2 2.1 1.9 1.7 ns xc4036xla 0.3 2.4 2.2 1.9 ns xc4044xla 0.3 2.7 2.4 2.2 ns xc4052xla 0.3 3.0 2.7 2.4 ns xc4062xla 0.3 3.3 3.0 2.7 ns xc4085xla 0.3 3.7 3.3 3.0 ns preliminary speed grade all -09 -08 -07 units description symbol device min max max max delay from pad through global early (ge) clock buffer to t ge xc4013xla 0.5 2.5 2.2 1.9 ns any iob clock input for bufges 3, 4, 7, and 8. xc4020xla 0.6 2.7 2.4 2.1 ns xc4028xla 0.6 2.9 2.5 2.3 ns xc4036xla 0.7 3.1 2.7 2.4 ns xc4044xla 0.8 3.3 2.9 2.6 ns xc4052xla 0.8 3.6 3.1 2.8 ns xc4062xla 0.9 3.8 3.4 3.0 ns xc4085xla 1.0 4.3 3.8 3.4 ns preliminary
r ds004 (v. 1.3) october 4, 1999 - product speci?cation 6-175 XC4000XLA/xv field programmable gate arrays 6 XC4000XLA clb characteristics testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all XC4000XLA devices and expressed in nanoseconds unless otherwise noted clb switching characteristic guidelines speed grade -09 -08 -07 units description symbol min max min max min max combinatorial delays f/g inputs to x/y outputs f/g inputs via h to x/y outputs f/g inputs via transparent latch to q outputs c inputs via sr/h0 via h to x/y outputs c inputs via h1 via h to x/y outputs c inputs via din/h2 via h to x/y outputs c inputs via ec, din/h2 to yq, xq output (bypass) t ilo t iho t ito t hh0o t hh1o t hh2o t cbyp 1.1 1.9 2.0 1.7 1.6 1.7 1.1 1.0 1.7 1.8 1.6 1.4 1.6 1.0 0.9 1.5 1.6 1.4 1.3 1.4 0.9 ns ns ns ns ns ns ns clb fast carry logic operand inputs (f1, f2, g1, g4) to c out add/subtract input (f3) to c out initialization inputs (f1, f3) to c out c in through function generators to x/y outputs c in to c out , bypass function generators carry net delay, c out to c in t opcy t ascy t incy t sum t byp t net 1.0 1.2 0.8 1.7 0.1 0.17 0.9 1.1 0.7 1.5 0.1 0.15 0.8 1.0 0.6 1.3 0.1 0.13 ns ns ns ns ns ns sequential delays clock k to flip-flop outputs q clock k to latch outputs q t cko t cklo 1.5 1.5 1.3 1.3 1.2 1.2 ns ns setup time before clock k f/g inputs f/g inputs via h c inputs via h0 through h c inputs via h1 through h c inputs via h2 through h c inputs via din c inputs via ec c inputs via s/r, going low (inactive) cin input via f/g cin input via f/g and h t ick t ihck t hh0ck t hh1ck t hh2ck t dick t ecck t rck t cck t chck 0.7 1.4 1.3 1.2 1.3 0.6 0.7 0.5 1.2 2.0 0.7 1.3 1.2 1.1 1.2 0.6 0.6 0.4 1.1 1.7 0.6 1.2 1.1 1.0 1.1 0.5 0.5 0.4 1.0 1.6 ns ns ns ns ns ns ns ns ns ns hold time after clock k all hold times 0.0 0.0 0.0 ns clock clock high time clock low time t ch t cl 2.2 2.2 1.9 1.9 1.7 1.7 ns ns set/reset direct width (high) delay from c inputs via s/r, going high to q t rpw t rio 2.3 2.5 2.3 2.2 2.3 2.0 ns ns global set/reset minimum gsr pulse width t mrw 12.8 11.4 10.2 ns delay from gsr input to any q t mrq see page 184 for trri values per device. toggle frequency (mhz) (for export control) f tog 227 263 294 mhz preliminary
r XC4000XLA/xv field programmable gate arrays 6-176 ds004 (v. 1.3) october 4, 1999 - product speci?cation clb single port ram synchronous (edge-triggered) write operation guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all XC4000XLA devices and are expressed in nanoseconds unless otherwise noted. single port ram speed grade -09 -08 -07 units size symbol min max min max min max write operation address write cycle time (clock k period) 16x2 32x1 t wcs t wcts 6.7 6.7 5.9 5.9 5.3 5.3 ns ns clock k pulse width (active edge) 16x2 32x1 t wps t wpts 3.4 3.4 3.0 3.0 2.7 2.7 ns ns address setup time before clock k 16x2 32x1 t ass t asts 1.5 1.5 1.3 1.3 1.2 1.2 ns ns address hold time after clock k 16x2 32x1 t ahs t ahts 0.0 0.0 0.0 0.0 0.0 0.0 ns ns din setup time before clock k 16x2 32x1 t dss t dsts 1.5 1.8 1.3 1.6 1.2 1.5 ns ns din hold time after clock k 16x2 32x1 t dhs t dhts 0.0 0.0 0.0 0.0 0.0 0.0 ns ns we setup time before clock k 16x2 32x1 t wss t wsts 1.4 1.3 1.3 1.2 1.1 1.1 ns ns we hold time after clock k 16x2 32x1 t whs t whts 0.0 0.0 0.0 0.0 0.0 0.0 ns ns data valid after clock k 16x2 32x1 t wos t wots 5.0 5.8 4.4 5.2 4.2 4.7 ns ns read operation address read cycle time 16x2 32x1 t rc t rct 2.6 3.8 2.6 3.8 2.6 3.8 ns ns data valid after address change (no write en- able) 16x2 32x1 t ilo t iho 1.1 1.9 1.0 1.7 0.9 1.5 ns ns address setup time before clock k 16x2 32x1 t ick t ihck 0.7 1.4 0.7 1.3 0.6 1.2 ns ns preliminary
r ds004 (v. 1.3) october 4, 1999 - product speci?cation 6-177 XC4000XLA/xv field programmable gate arrays 6 clb dual port ram synchronous (edge-triggered) write operation guidelines clb ram synchronous (edge-triggered) write timing waveforms dual port ram speed grade -09 -08 -07 units size symbol min max min max min max address write cycle time (clock k period) 16x1 t wcds 6.7 5.9 5.3 ns clock k pulse width (active edge) 16x1 t wpds 3.4 3.0 2.7 ns address setup time before clock k 16x1 t asds 1.5 1.3 1.2 ns address hold time after clock k 16x1 t ahds 0.0 0.0 0.0 ns din setup time before clock k 16x1 t dsds 1.7 1.6 1.4 ns din hold time after clock k 16x1 t dhds 0.0 0.0 0.0 ns we setup time before clock k 16x1 t wsds 1.4 1.3 1.1 ns we hold time after clock k 16x1 t whds 0.0 0.0 0.0 ns data valid after clock k 16x1 t wods 5.7 5.1 4.6 ns note: timing for 16x1 option is identical to 16x2 ram. preliminary x6461 wclk (k) we address data in data out old new t dss t dhs t ass t ahs t wss t wps t whs t wos t ilo t ilo dual port ram single port ram wclk (k) we address data in t dsds t dhds t asds t ahds t wsds t wpds t whds x6474 data out old new t wods t ilo t ilo
r XC4000XLA/xv field programmable gate arrays 6-178 ds004 (v. 1.3) october 4, 1999 - product speci?cation XC4000XLA pin-to-pin output parameter guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% func- tionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaran- teed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ect- ing the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development sys- tem) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanoseconds unless otherwise noted. global clock input to output delay fastclk input to output delay for bufnw, bufsw, bufne, & bufse speed grade all -09 -08 -07 units description symbol device min max max max global low skew (gls) clock input to output delay us- ing output flip-flop t ickof xc4013xla 1.2 5.6 5.0 4.5 ns xc4020xla 1.3 5.8 5.2 4.7 ns xc4028xla 1.4 6.1 5.5 4.9 ns xc4036xla 1.4 6.4 5.7 5.1 ns xc4044xla 1.5 6.8 6.0 5.4 ns xc4052xla 1.6 7.1 6.3 5.7 ns xc4062xla 1.6 7.4 6.6 5.9 ns xc4085xla 1.6 8.2 7.3 6.5 ns for output slow option add t slow all devices 0.5 1.7 1.6 1.4 ns preliminary notes: listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb ?ip-?ops are clocked by the global clock net. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1 . speed grade all -09 -08 -07 units description symbol device min max max max fastclk input to output delay using output flip-flop for fastclk buffers bufnw, bufsw, bufne, and bufse. t ickfof xc4013xla 1.0 4.6 4.1 3.7 ns xc4020xla 1.0 4.7 4.2 3.7 ns xc4028xla 1.0 4.8 4.3 3.8 ns xc4036xla 1.1 4.9 4.4 3.9 ns xc4044xla 1.1 5.0 4.4 4.0 ns xc4052xla 1.1 5.1 4.5 4.1 ns xc4062xla 1.1 5.2 4.6 4.1 ns xc4085xla 1.1 5.4 4.8 4.3 ns preliminary notes: listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb ?ip-?ops are clocked by the global clock net. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1 .
r ds004 (v. 1.3) october 4, 1999 - product speci?cation 6-179 XC4000XLA/xv field programmable gate arrays 6 global early clock input to output delay for bufge #s 1, 2, 5, and 6 global early clock input to output delay for bufge #s 3, 4, 7, and 8 capacitive load factor figure 1 shows the relationship between i/o output delay and load capacitance. it allows a user to adjust the speci- ?ed output delay if the load capacitance is different than 50 pf. for example, if the actual load capacitance is 120 pf, add 2.5 ns to the speci?ed delay. if the load capac- itance is 20 pf, subtract 0.8 ns from the speci?ed output delay. figure 1 is usable over the speci?ed operating conditions of voltage and temperature and is independent of the output slew rate control. figure 1: delay factor at various capacitive loads speed grade all -09 -08 -07 units description symbol device min max max max global clock signal input to output delay using global early (ge) clock buffer to clock output flip-flop for bufge #s 1, 2, 5, & 6. t ickeof xc4013xla 0.8 4.9 4.4 3.9 ns xc4020xla 0.8 5.1 4.6 4.1 ns xc4028xla 0.8 5.3 4.8 4.3 ns xc4036xla 0.8 5.6 5.1 4.5 ns xc4044xla 0.9 5.9 5.3 4.8 ns xc4052xla 0.9 6.2 5.6 5.0 ns xc4062xla 0.9 6.5 5.9 5.3 ns xc4085xla 0.9 6.9 6.2 5.6 ns preliminary notes: listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb ?ip-?ops are clocked by the global clock net. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1 . speed grade all -09 -08 -07 units description symbol device min max max max global clock signal input to output delay using global early (ge) clock buffer to clock output flip-flop for bufge #s 3, 4, 7, & 8. t ickeof xc4013xla 1.1 5.7 5.1 4.5 ns xc4020xla 1.1 5.9 5.3 4.7 ns xc4028xla 1.2 6.1 5.4 4.9 ns xc4036xla 1.3 6.3 5.6 5.0 ns xc4044xla 1.3 6.5 5.8 5.2 ns xc4052xla 1.4 6.8 6.0 5.4 ns xc4062xla 1.5 7.0 6.3 5.6 ns xc4085xla 1.6 7.5 6.7 6.0 ns preliminary notes: listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb ?ip-?ops are clocked by the global clock net. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1 . x8257 -2 0 20406080 capacitance (pf) delta delay (ns) 100 120 140 -1 0 1 2 3
r XC4000XLA/xv field programmable gate arrays 6-180 ds004 (v. 1.3) october 4, 1999 - product speci?cation XC4000XLA pin-to-pin input parameter guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanoseconds unless otherwise noted. global low skew clock, set-up and hold speed grade -09 -08 -07 units description symbol device min min min input setup and hold time relative to global clock input signal no delay xc4013xla 1.0 / 3.0 0.8 / 2.6 0.2 / 2.5 ns global low skew clock and iff t psn /t phn xc4020xla 0.9 / 3.2 0.7 / 2.9 0.1 / 2.7 ns xc4028xla 0.8 / 3.8 0.6 / 3.3 0.0 / 3.0 ns xc4036xla 0.6 / 4.0 0.4 / 3.5 0.0 / 3.3 ns xc4044xla 0.4 / 4.4 0.2 / 3.9 0.0 / 3.6 ns xc4052xla 0.3 / 4.6 0.2 / 4.1 0.0 / 3.9 ns xc4062xla 0.2 / 5.0 0.1 / 4.5 0.0 / 4.2 ns xc4085xla 0.0 / 5.4 0.0 / 4.8 0.0 / 4.5 ns partial delay xc4013xla 4.4 / 0.5 4.1 / 0.3 3.7/ 0.0 ns global low skew clock and iff t psp /t php xc4020xla 4.5 / 0.6 4.1 / 0.3 3.7 / 0.0 ns xc4028xla 4.6 / 0.7 4.2 / 0.4 3.7/ 0.0 ns xc4036xla 4.6 / 0.8 4.2 / 0.4 3.7/ 0.0 ns xc4044xla 4.7 / 0.9 4.3 / 0.5 3.8 / 0.0 ns xc4052xla 4.8 / 1.0 4.3 / 0.6 3.8 / 0.2 ns xc4062xla 5.0 / 1.0 4.4 / 0.7 3.8 / 0.4 ns xc4085xla 5.5 / 1.2 4.7 / 0.9 3.8 / 0.5 ns full delay xc4013xla 4.4 / 0.0 4.1 / 0.0 3.7 / 0.0 ns global low skew clock and iff t psd /t phd xc4020xla 4.6 / 0.0 4.2 / 0.0 3.8 / 0.0 ns xc4028xla 4.8 / 0.0 4.4 / 0.0 3.9 / 0.0 ns xc4036xla 4.9 / 0.0 4.5 / 0.0 4.0 / 0.0 ns xc4044xla 5.0 / 0.0 4.6 / 0.0 4.1 / 0.0 ns xc4052xla 5.2 / 0.0 4.7 / 0.0 4.2 / 0.0 ns xc4062xla 5.5 / 0.0 4.9 / 0.0 4.3 / 0.0 ns xc4085xla 6.0 / 0.0 5.2/ 0.0 4.4 / 0.0 ns iff = input flip-flop or latch preliminary note: setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is measured relative to the global clock input signal using the furthest distance and a reference load of one clock pin per two iobs. use the static timing analyzer (trce) to determine the setup and hold times under given design conditions.
r ds004 (v. 1.3) october 4, 1999 - product speci?cation 6-181 XC4000XLA/xv field programmable gate arrays 6 fastclk input set-up and hold for bufnw, bufsw, bufne, & bufse speed grade -09 -08 -07 units description symbol device min min min input setup and hold time relative to fastclk input signal no delay xc4013xla 0.0 / 3.2 0.0 / 2.9 0.0 / 2.6 ns fastclk and iff t psfn /t phfn xc4020xla 0.0 / 3.3 0.0 / 3.0 0.0 / 2.7 ns xc4028xla 0.0 / 3.4 0.0 / 3.1 0.0 / 2.8 ns xc4036xla 0.0 / 3.5 0.0 / 3.2 0.0 / 2.9 ns xc4044xla 0.0 / 3.6 0.0 / 3.3 0.0 / 3.0 ns xc4052xla 0.0 / 3.7 0.0 / 3.4 0.0 / 3.1 ns xc4062xla 0.0 / 3.8 0.0 / 3.5 0.0 / 3.2 ns xc4085xla 0.0 / 3.9 0.0 / 3.6 0.0 / 3.3 ns partial delay xc4013xla 3.5 / 0.6 3.2 / 0.3 2.9 / 0.0 ns fastclk and iff t psfp t phfp xc4020xla 3.7 / 0.4 3.4 / 0.2 3.1 / 0.0 ns xc4028xla 3.9 / 0.2 3.6 / 0.1 3.3 / 0.0 ns xc4036xla 4.1 / 0.0 3.8 / 0.0 3.5 / 0.0 ns xc4044xla 4.3 / 0.0 4.0 / 0.0 3.7 / 0.0 ns xc4052xla 4.5 / 0.0 4.2 / 0.0 3.9 / 0.0 ns xc4062xla 4.7 / 0.0 4.4 / 0.0 4.1 / 0.0 ns xc4085xla 5.1 / 0.0 4.8 / 0.0 4.5 / 0.0 ns full delay xc4013xla 3.5 / 0.6 3.2 / 0.3 2.9 / 0.0 ns fastclk and iff t psfd /t phfd xc4020xla 3.8 / 0.4 3.5 / 0.2 3.2 / 0.0 ns xc4028xla 4.0 / 0.2 3.7 / 0.1 3.4 / 0.0 ns xc4036xla 4.3 / 0.0 4.0 / 0.0 3.7 / 0.0 ns xc4044xla 4.6 / 0.0 4.3 / 0.0 4.0 / 0.0 ns xc4052xla 4.9 / 0.0 4.6 / 0.0 4.3 / 0.0 ns xc4062xla 5.3 / 0.0 5.0 / 0.0 4.7 / 0.0 ns xc4085xla 6.1 / 0.0 5.8 / 0.0 5.5 / 0.0 ns iff = input flip-flop or latch preliminary note: setup time is measured with the fastest route and the lightest load. hold time is measured using the furthest distance and a reference load of one clock pin per two iobs. use the static timing analyzer (trce)) to determine the setup and hold times under given design conditions.
r XC4000XLA/xv field programmable gate arrays 6-182 ds004 (v. 1.3) october 4, 1999 - product speci?cation bufge #s 1, 2, 5, and 6 global early clock, set-up and hold for iff and fcl testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanoseconds unless otherwise noted. speed grade -09 -08 -07 units description symbol device min min min input setup and hold time relative to global clock input signal no delay xc4013xla 1.0 / 3.2 0.8 / 2.6 0.5 / 1.8 ns global early clock and iff t psen /t phen xc4020xla 1.0 / 3.4 0.8 / 2.8 0.5 / 2.0 ns global early clock and fcl t pfsen /t pfhen xc4028xla 1.0 / 3.5 0.8 / 3.0 0.5 / 2.2 ns xc4036xla 1.0 / 3.6 0.8 / 3.1 0.5 / 2.4 ns xc4044xla 1.0 / 3.8 0.8 / 3.3 0.5 / 2.6 ns xc4052xla 1.0 / 4.0 0.8 / 3.5 0.5 / 2.8 ns xc4062xla 1.0 / 4.2 0.8 / 3.7 0.5 / 3.0 ns xc4085xla 1.0 / 4.6 0.8 / 4.0 0.5 / 3.2 ns partial delay xc4013xla 4.6 / 0.0 4.2 / 0.0 3.9 / 0.0 ns global early clock and iff t psep /t phep xc4020xla 4.8 / 0.1 4.4 / 0.1 4.1 / 0.0 ns global early clock and fcl t pfsep /t pfhep xc4028xla 4.9 / 0.1 4.6 / 0.1 4.4 / 0.0 ns xc4036xla 5.0 / 0.2 4.7 / 0.1 4.5 / 0.0 ns xc4044xla 5.5 / 0.3 5.1 / 0.2 4.8 / 0.0 ns xc4052xla 5.8 / 0.3 5.3 / 0.2 5.0 / 0.0 ns xc4062xla 6.2 / 0.4 5.6 / 0.2 5.2 / 0.0 ns xc4085xla 6.5 / 0.5 5.9 / 0.3 5.4 / 0.0 ns full delay xc4013xla 4.6 / 0.0 4.2 / 0.0 3.9 / 0.0 ns global early clock and iff t psed /t phed xc4020xla 4.9 / 0.0 4.5 / 0.0 4.1 / 0.0 ns xc4028xla 5.1 / 0.0 4.7 / 0.0 4.4 / 0.0 ns xc4036xla 5.3 / 0.0 4.9 / 0.0 4.5 / 0.0 ns xc4044xla 5.8 / 0.0 5.3 / 0.0 5.0 / 0.0 ns xc4052xla 6.2 / 0.0 5.7 / 0.0 5.3 / 0.0 ns xc4062xla 6.7 / 0.0 6.1 / 0.0 5.6 / 0.0 ns xc4085xla 7.0 / 0.0 6.4 / 0.0 6.0 / 0.0 ns iff = input flip-flop or latch, fcl = fast capture latch preliminary note: setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is measured relative to the global clock input signal using the furthest distance and a reference load of one clock pin per two iobs. use the static timing analyzer (trce) to determine the setup and hold times under given design conditions.
r ds004 (v. 1.3) october 4, 1999 - product speci?cation 6-183 XC4000XLA/xv field programmable gate arrays 6 bufge #s 3, 4, 7, and 8 global early clock, set-up and hold for iff and fcl speed grade -09 -08 -07 units description symbol device min min min input setup and hold time relative to global clock input signal no delay xc4013xla 0.8 / 3.2 0.6 / 2.6 0.4 / 2.0 ns global early clock and iff t psen /t phen xc4020xla 0.8 / 3.4 0.6 / 2.8 0.4 / 2.2 ns global early clock and fcl t pfsen /t pfhen xc4028xla 0.8 / 3.5 0.6 / 3.0 0.4 / 2.4 ns xc4036xla 0.8 / 3.6 0.6 / 3.1 0.4 / 2.6 ns xc4044xla 0.8 / 3.8 0.6 / 3.3 0.4 / 2.8 ns xc4052xla 0.8 / 4.0 0.6 / 3.5 0.4 / 3.0 ns xc4062xla 0.8 / 4.2 0.6 / 3.7 0.4 / 3.2 ns xc4085xla 0.8 / 4.6 0.6 / 4.0 0.4 / 3.4 ns partial delay xc4013xla 4.4 / 0.0 4.0 / 0.0 3.6 / 0.0 ns global early clock and iff t psep /t phep xc4020xla 4.6 / 0.1 4.2 / 0.1 3.8 / 0.0 ns global early clock and fcl t pfsep /t pfhep xc4028xla 4.7 / 0.1 4.4 / 0.1 4.1 / 0.0 ns xc4036xla 4.8 / 0.2 4.5 / 0.2 4.2 / 0.0 ns xc4044xla 5.2 / 0.3 4.8 / 0.3 4.4 / 0.0 ns xc4052xla 5.6 / 0.3 5.1 / 0.3 4.6 / 0.0 ns xc4062xla 6.0 / 0.4 5.4 / 0.4 4.8 / 0.0 ns xc4085xla 6.3 / 0.5 5.7 / 0.5 5.0 / 0.0 ns full delay xc4013xla 4.4 / 0.0 4.0 / 0.0 3.6 / 0.0 ns global early clock and iff t psed /t phed xc4020xla 4.7 / 0.0 4.3 / 0.0 3.8 / 0.0 ns xc4028xla 4.9 / 0.0 4.5 / 0.0 4.1 / 0.0 ns xc4036xla 5.1 / 0.0 4.7 / 0.0 4.2 / 0.0 ns xc4044xla 5.6 / 0.0 5.1 / 0.0 4.6 / 0.0 ns xc4052xla 6.0 / 0.0 5.5 / 0.0 4.9 / 0.0 ns xc4062xla 6.5 / 0.0 5.9 / 0.0 5.2 / 0.0 ns xc4085xla 6.8 / 0.0 6.2 / 0.0 5.6 / 0.0 ns iff = input flip-flop or latch, fcl = fast capture latch preliminary note: setup time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is measured relative to the global clock input signal using the furthest distance and a reference load of one clock pin per two iobs. use the static timing analyzer (trce) to determine the setup and hold times under given design conditions.
r XC4000XLA/xv field programmable gate arrays 6-184 ds004 (v. 1.3) october 4, 1999 - product speci?cation iob input switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). iob input delay guidelines speed grade -09 -08 -07 units description symbol device min max min max min max clocks clock enable (ec) to clock (ik) t ecik all devices 0.0 0.0 0.0 ns delay from fcl enable (ok) active edge to iff clock (ik) active edge t okik all devices 1.4 1.3 1.2 ns setup times pad to clock (ik), no delay t pick all devices 1.2 1.0 0.9 ns pad to clock (ik), via transparent fast capture latch, no delay t pickf all devices 1.6 1.4 1.3 ns pad to fast capture latch enable (ok), no de- lay t pock all devices 0.8 0.7 0.6 ns hold times all hold times all devices 0.0 0.0 0.0 ns global set/reset minimum gsr pulse width t mrw all devices 12.8 11.4 10.2 ns global set/reset delay from gsr input to any q t rri* xc4013xla 11.4 10.2 9.1 ns xc4020xla 13.3 11.9 10.6 ns xc4028xla 14.3 12.8 11.4 ns xc4036xla 16.2 14.5 12.9 ns xc4044xla 18.1 16.2 14.4 ns xc4052xla 19.5 17.4 15.6 ns xc4062xla 20.9 18.7 16.7 ns xc4085xla 24.7 22.1 19.7 ns propagation delays pad to i1, i2 t pid all devices 1.0 0.9 0.8 ns pad to i1, i2 via transparent input latch, no de- lay t pli all devices 2.1 1.9 1.7 ns pad to i1, i2 via transparent fcl and input latch, no delay t pfli all devices 2.5 2.2 2.0 ns clock (ik) to i1, i2 (flip-flop) t ikri all devices 1.1 1.0 0.9 ns clock (ik) to i1, i2 (latch enable, active low) t ikli all devices 1.2 1.1 1.0 ns fcl enable (ok) active edge to i1, i2 (via transparent standard input latch) t okli all devices 2.4 2.1 1.9 ns iff = input flip-flop or latch, fcl = fast capture latch preliminary * indicates minimum amount of time to assure valid data.
r ds004 (v. 1.3) october 4, 1999 - product speci?cation 6-185 XC4000XLA/xv field programmable gate arrays 6 xla iob output switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). for propagation delays, slew-rate = fast unless otherwise noted. values are expressed in nanoseconds unless otherwise noted. speed grade -09 -08 -07 units description symbol device min max min max min max clocks clock high t ch all devices 2.2 1.9 1.7 ns clock low t cl all devices 2.2 1.9 1.7 ns propagation delays clock (ok) to pad t okpof all devices 3.2 2.9 2.6 ns output (o) to pad t opf all devices 2.6 2.4 2.1 ns 3-state to pad hi-z (slew-rate independent) t tshz all devices 2.7 2.4 2.2 ns 3-state to pad active and valid t tsonf all devices 2.8 2.5 2.3 ns clock to pad hi-z t okshz all devices 3.5 3.1 2.8 ns clock to pad active and valid t oksonf all devices 3.6 3.2 2.9 ns output (o) to pad via fast output mux t ofpf all devices 3.6 3.2 2.9 ns select (ok) to pad via fast mux t okfpf all devices 3.3 3.0 2.6 ns setup and hold times output (o) to clock (ok) setup time t ook all devices 0.3 0.3 0.3 ns output (o) to clock (ok) hold time t oko all devices 0.0 0.0 0.0 ns clock enable (ec) to clock (ok) setup time t ecok all devices 0.0 0.0 0.0 ns clock enable (ec) to clock (ok) hold time t okec all devices 0.0 0.0 0.0 ns global set/reset minimum gsr pulse width t mrw 12.8 11.4 10.2 ns delay from gsr input to any pad t rpo* xc4013xla 14.4 12.8 11.5 ns xc4020xla 16.3 14.5 13.0 ns xc4028xla 17.3 15.4 13.8 ns xc4036xla 19.1 17.1 15.3 ns xc4044xla 21.0 18.8 16.8 ns xc4052xla 22.5 20.1 17.9 ns xc4062xla 23.9 21.3 19.0 ns xc4085xla 27.7 24.7 22.1 ns slew rate adjustment for output slow option add t slow 1.7 1.6 1.4 ns * indicates minimum amount of time to assure valid data preliminary
r XC4000XLA/xv field programmable gate arrays 6-186 ds004 (v. 1.3) october 4, 1999 - product speci?cation revision control version description 1/28/99 (1.0) release included in 1999 data book, section 6 2/19/99 (1.1) updated switching characteristics tables 5/14/99 (1.2) replaced electrical specification pages for xla and xv families with separate updates and added url link on placeholder page for electrical specifications/pinouts for weblinx users. 10/4/99 (1.3) added power-on specification.

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